cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 1/9 mtb1k0n20kl3 preliminary cys tek product specification n-channel enhancement mode mosfet mtb1k0n20kl3 bv dss 200v features i d @ v gs =10v, t a =25 c 1a r dson @v gs =10v, i d =2a 830m (typ.) 777m (typ.) r dson @v gs =4.5v, i d =1a ? low gate charge ? simple drive requirement ? esd protected gate, hbm 6kv, typically ? pb-free lead plating & halogen-free package equivalent circuit outline mtb1k0n20kl3 sot-223 d s g gate d drain s source d g ordering information device package shipping sot-223 MTB1K0N20KL3-0-T3-G 2500 pcs / tape & reel (pb-free lead plating & halogen-free package) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t3 : 2500 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 2/9 mtb1k0n20kl3 preliminary cys tek product specification absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 200 gate-source voltage v gs 20 v continuous drain current @ t a =25 c, v gs =10v 1 continuous drain current @ t a =70 c, v gs =10v i d 0.8 pulsed drain current *1 i dm 4 avalanche current @ l=0.1mh i as 2 a avalanche energy @ l=1mh, i d =2a, v dd =50v *2 e as 2 repetitive avalanche energy @ l=0.05mh e ar 0.625 mj esd susceptibility *3 v esd 6000 v total power dissipation @t a =25 2.4 total power dissipation @t a =70 p d 1.5 w operating junction and storage temperature range tj, tstg -55~+150 c note : *1 . pulse width limited by maximum junction temperature *2. guaranteed by design, not by 100% test. *3. human body model, 1.5k in series with 100pf thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 10 thermal resistance, junction-to-ambient, max r ja 52 (note) c/w note : when mounted on a 1 in 2 pad of 2 oz. copper. characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 200 - - v gs =0v, i d =250 a v gs(th) 1 - 3 v v ds =v gs , i d =250 a g fs *1 - 3.1 - s v ds =10v, i d =1a i gss - - 10 v gs = 16v, v ds =0v - - 1 v ds =160v, v gs =0v i dss - - 25 a v ds =160v, v gs =0v, tj=125 c - 0.83 1.08 v gs =10v, i d =2a r ds(on) *1 - 0.78 1.6 v gs =4.5v, i d =1a dynamic qg *1, 2 - 5.2 7.8 qgs *1, 2 - 1 1.5 qgd *1, 2 - 2.8 4.2 nc v ds =150v, v gs =5v, i d =3.6a t d(on) *1, 2 - 39 58.5 tr *1, 2 - 80.4 120.6 t d(off) *1, 2 - 94.2 141.3 t f *1, 2 - 59.2 88.8 ns v ds =100v, i d =3.6a, v gs =5v, r g =25
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 3/9 mtb1k0n20kl3 preliminary cys tek product specification ciss - 273 409.5 coss - 21 31.5 crss - 23 34.5 pf v gs =0v, v ds =30v, f=1mhz source-drain diode i s *1 - - 1 i sm *3 - - 4 a v sd *1 - 0.8 1 v i s =1a, v gs =0v trr - 46.8 - ns qrr - 72.2 - nc i f =3.6a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. recommended soldering footprint
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 4/9 mtb1k0n20kl3 preliminary cys tek product specification typical characteristics typical output characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 024681 0 brekdown voltage vs junction temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v v ds , drain-source voltage(v) i d , drain current (a) 10v,9v,8v,7v,6v,5v,4.5v,4v,3.5v 3v v =2.5v gs static drain-source on-state resistance vs drain current 100 1000 0.01 0.1 1 10 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =4.5v 10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 00.511.522.533.54 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 800 850 900 950 1000 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalizedstatic drain-source on-state resistance v gs =10v, i d =2a r dson @tj=25c : 830m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =2a
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 5/9 mtb1k0n20kl3 preliminary cys tek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 1 10 100 1000 0 102030405060708090100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.5 0.7 0.9 1.1 1.3 1.5 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =15v v ds =10v gate charge characteristics 0 2 4 6 8 10 0246810 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =40v v ds =150v i d =3.6a maximum safe operating area 0.001 0.01 0.1 1 10 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) r ds(on) limited dc 10ms 100ms 1ms 100 s 10 s t a =25c, tj=150c, v gs =10v, r ja =52c/w, single pulse maximum drain current vs junction temperature 0 0.2 0.4 0.6 0.8 1 1.2 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) v gs =10v, r ja =52c/w
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 6/9 mtb1k0n20kl3 preliminary cys tek product specification typical characteristics(cont.) typical transfer characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 012345 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse power rating, junction to ambient (note on page 2) 0 10 20 30 40 50 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =150c t a =25c r ja =52c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =52c/w
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 7/9 mtb1k0n20kl3 preliminary cys tek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 8/9 mtb1k0n20kl3 preliminary cys tek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c043l3 issued date : 2017.07.03 revised date : 2017.07.20 page no. : 9/9 mtb1k0n20kl3 preliminary cys tek product specification sot-223 dimension *: typical inches millimeters 321 f b a c d e g h a1 a2 i style: pin 1.gate 2.drain 3.source marking: 3-lead sot-223 plastic surface mounted package cystek package code: l3 device name date code b1k0n20k 1 2 3 inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1142 0.1220 2.90 3.10 g 0.0551 0.0709 1.40 1.80 b 0.2638 0.2874 6.70 7.30 h 0.0098 0.0138 0.25 0.35 c 0.1299 0.1457 3.30 3.70 i 0.0008 0.0039 0.02 0.10 d 0.0236 0.0315 0.60 0.80 a1 *13 o - *13 o - e *0.0906 - *2.30 - a2 0 o 10 o 0 o 10 o f 0.2480 0.2638 6.30 6.70 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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